1. Field of the Invention
The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device such as a NOR---type electrically erasable and programmable readonly memory (EEPROM).
2. Description of the Related Art
Generally, an EEPROM cell includes a P-type semiconductor substrate having an N.sup.+ -type source region, an N.sup.+ -type drain region, a floating gate electrode via a first gate insulating layer, and a control gate electrode via a second insulating layer on the floating gate electrode.
In a NOR-type nonvolatile semiconductor memory device by using the above-described EEPROM cells, a plurality of word lines, a plurality of bit lines, and a plurality of source lines are provided, and each of the EEPROM cells has a control gate electrode connected to one of the word lines, a source connected to one of the source lines, and a drain connected to one of the bit lines. For example, the source lines are connected to a source circuit. Therefore, a plurality of the source regions are usually electrically connected to each other.
In a prior art method for manufacturing a NOR-type semiconductor memory device (see JP-A-HEI 3-211775), a plurality of field areas in parallel with each other along a first direction, a plurality of electrode areas in parallel with each other along a second direction approximately perpendicular to the first direction, a plurality of source areas surrounded by the field areas and the electrode areas, and a plurality of drain areas surrounded by the field areas and the electrode areas are provided in a semiconductor substrate. In this case, the source areas and the drain areas are alternately arranged with respect to the electrode areas. First, a plurality of thick insulating layers, so called field insulating layers, are formed in the field areas. Then, electrodes each formed by a floating gate electrode and a control gate electrode are formed in the electrode areas. Then, only the thick insulating layers between the source areas are etched. Finally, impurities are introduced not only into the source reas and the drain areas but also into the field areas between the source regions. As a result, all the source regions are electrically connected to each other. This will be explained later in detail.
In the above-described prior art method, however, the source areas of the semiconductor substrate are overetched simultaneously with etching of the field insulating layers therebetween. As a result, the source areas of the semiconductor substrate are damaged which invites a deterioration of characteristics.